This invention relates to the structure and operation of BiCMOS static memories.
Basically, a BiCMOS memory is a memory which is made of both bipolar transistors and field effect transistors. One such memory is described, for example, in U.S. Pat. No. 4,984,203 (hereinafter U.S. Pat. No. '203) issued Jan. 8, 1991 which is assigned to the present assignee.
Included in the memory of U.S. Pat. No. '203 is a rowcolumn array of memory cells. Each cell is made entirely of field effect transistors which are cross-coupled to each other. On the other hand, bipolar transistors are used in the memory to read data from the cells.
Field effect transistors are inherently smaller in size than bipolar transistors, and thus the memory cells of U.S. Pat. No. '203 have a high packing density. By comparison, bipolar transistors have a faster switching speed than field-effect transistors, and thus the memory of U.S. Pat. No. '203 has a high read speed.
However, one drawback which the U.S. Pat. No. '203 memory has is that the "1" voltage level within each memory cell is not fixed. Instead, only the "0" voltage level is fixed by a supply voltage on the source of the memory cell transistors Q1 and Q2; and, the "1" voltage moves up and down with the select and deselect voltages that are applied by the select lines to the drain of the cell transistors Q3 and Q4. This up and down movement of the "1" voltage level limits the degree to which the "0" voltage can be shifted towards the "1" voltage before errors due to noise start to occur.
Suppose, for example, that the "1" voltage level switches between -1.0 volts and -1.6 volts as shown in FIG. 2 of U.S. Pat. No. '203, and suppose that the "0" voltage is shifted from -5.2 volts to -3.4 volts. Such a shift in the "0" voltage level would be desirable in order to reduce the voltage across the cell transistors Q1-Q4 and thereby allow those transistors to be scaled down in size.
In the above example, when a cell is selected, the "1" voltage differs from the "0" voltage by 3.4 volts minus 1.0 volts or 2.4 volts. However, when a cell is deselected, the "1" voltage differs from the "0" voltage by only 3.4 volts minus 1.6 volts or 1.8 volts. This reduction in the difference between a "1" and "0" voltage increases the cell's susceptible to errors due to noise,--i.e. it reduces the cell's noise margin.
An additional limitation of U.S. Pat. No. '203 memory is that the memory cells cannot accommodate more than two read ports. This is because in U.S. Pat. No. '203, only one read port can be connected to the set node S of a cell and only one read port can be connected to the reset node R of a cell.
Accordingly, a primary object of the present invention is to provide a novel BiCMOS memory which has a high speed, a high cell density, a low susceptibility to noise as the "1" and "0" voltage levels approach each other, and can accommodate more than two read ports.